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acpl-w70l-000e and acpl-k73l-000e single-channel and dual-channel high speed 15 mbd cmos optocoupler with glitch-free power-up feature data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-w70l (single-channel) and acpl-k73l (dual- channel) are 15 mbd cmos optocouplers in ssoic-6 and ssoic-8 package respectively. the optocouplers utilize the latest cmos ic technology to achieve outstanding perfor - mance with very low power consumption. basic building blocks of acpl-w70l and acpl-k73l are high speed leds and cmos detector ics. each detector incorporates an in - tegrated photodiode, a high speed transimpedance am - plifer, and a voltage comparator with an output driver. component image features ? +3.3v and 5 v cmos compatibility ? 25ns max. pulse width distortion ? 55ns max. propagation delay ? 40ns max. propagation delay skew ? high speed: 15 mbd min ? 10 kv/s minimum common mode rejection ? C40 to 105c temperature range ? glitch-free power-up feature ? safety and regulatory approvals: - ul recognized: 5000 v rms for 1 min. per ul 1577 option 020 - csa component acceptance notice #5 - iec/en/din en 60747-5-2 approved option 060 (pending) applications ? digital feld bus isolation: - canbus, rs485, usb ? multiplexed data transmission ? computer peripheral interface ? microprocessor system interface ? dc/dc converter a 0.1 f bypass capacitor must be connected between pins 4 and 6 for acpl-w70l and pins 5 and 8 for acpl-k73l. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product t r u t h t a b l e l e d v o , o u t p u t o f f l o n h a c p l - w 7 0 l a c p l - k 7 3 l 2 3 6 4 1 5 n c * a n o d e c a t h o d e v d d g n d v o s h i e l d 5 6 7 8 4 3 2 1 v d d v o 1 a n o d e 1 c a t h o d e 1 v o 2 g n d a n o d e 2 c a t h o d e 2 s h i e l d
2 ordering information acpl-w70l and acpl-k73l will be ul recognized with 3750 v rms for 1 minute per ul1577. part number option package surface mount gull wing tape& reel ul 5000 v rms / 1 minute rating iec/en/din en 60747-5-2 quantity rohs compliant acpl-w70l -000e sso-6 x 100 per tube -500e x x 1000 per reel -020e x x 100 per tube -520e x x x 1000 per reel -060e x x 100 per tube -560e x x x 1000 per reel acpl-k73l -000e sso-8 x 80 per tube -500e x x 1000 per reel -020e x x 80 per tube -520e x x x 1000 per reel -060e x x 80 per tube -560e x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-w70l-500e to order product of stretched so-6 package in tape and reel packaging in rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 package dimensions acpl-w70l (stretched so-6 package) acpl-k73l (stretched s0-8 package) 4.580 0.180 45 0.381 0.127 (0.015 0.005) 1.27 (0.050) bsg 0.20 0.10 (0.008 0.004) 0.45 (0.018) 0.750 0.250 (0.0295 0.010) 11.50 0.250 (0.453 0.010) 6.807 0.268 dimensions in millimeters (inches). lead coplanarity = 0.1 mm (0.004 inches). 7 12.65 (0.498) land pattern recommendation 3.180 0.127 (0.125 0.005) 1.590 0.127 (0.063 0.005) 7 1.91 (0.075) 3 2 1 4 5 6 0.76 (0.030) +0.254 0 +0.010 - 0.000 +0.127 0 +0.005 - 0.000 ) ( ) ( 4 0.381 0.13 (0.015 0.005) 1.270 (0.050) bsg dimensions in millimeters (inches). lead coplanarity = 0.1 mm (0.004 inches). 12.650 (0.5) 7 1.905 (0.1) 3 2 1 5 6 7 8 45 0.200 0.100 (0.008 0.004) 0.450 (0.018) 0.750 0.250 (0.0295 0.010) 11.5 0.250 (0.453 0.010) 6.807 0.127 (0.268 0.005) 7 3.180 0.127 (0.125 0.005) 1.590 0.127 (0.063 0.005) 5.850 0.230 +0.25 0 +0.010 - 0.000 ) ( land pattern recommendation
4 note: non-halide fux should be used. 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160c 140c 150c peak temp. 245c peak temp. 240c peak temp. 230c soldering time 200c preheating time 150c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1c/?0.5c tight typical loose room temperature preheating rate 3c + 1c/?0.5c/sec. reflow heating rate 2.5c 0.5c/sec. solder refow thermal profle regulatory information the acpl-w70l and acpl-k73l are approved by the fol - lowing organizations: ul recognized under ul 1577, component recognition pro - gram, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 60747-5-2 pending approval under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884teil 2):2003-01 (option 060 only) 217 c ramp-down 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c non-halide ux should be used recommended pb-free ir profle
5 all avago technologies data sheets report the creepage and clearance inherent to the optocoupler component it - self. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specifed for individual equipment standards. for creepage, the shortest distance iec/en/din en 60747-5-2 insulation characteristics* description symbol option 060 units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 450 v rms for rated mains voltage 600 v rms for rated mains voltage 1000 v rms i C iv i - iii i C iii i C iii i C iii climatic classifcation 55/105/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 1140 v peak input to output test voltage, method b ** v iorm x 1.875=v pr, 100% production test with t m =1 sec, partial discharge < 5 pc v pr 2137 v peak input to output test voltage, method a ** v iorm x 1.5=v pr, type and sample test, t m =60 sec, partial discharge < 5 pc v pr 1710 v peak highest allowable overvoltage (transient overvoltage t ini = 10 sec) v iotm 6000 v peak safety-limiting values C maximum values allowed in the event of a failure, also see figure 2. case temperature input current output power t s i s, input p s, output 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r io >109 w note: * isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. surface mount classifcation is class a in accordance with ceccoo802. ** refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section iec/en/ din en 60747-5-2, for a detailed description of method a and method b partial discharge test profles. these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. the surface mount classifcation is class a in accordance with cecc 00802. parameter symbol value units conditions minimum external air gap (clearance) l(i01) 8.0 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(i02) 8.0 mm measured from input terminals to output ter - minals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm insulation thickness between emitter and detector; also known as distance through insulation. tracking resistance (comparative tracking index) cti 175 volts din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) path along the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
6 absolute maximum ratings parameter symbol min. max. units storage temperature t s C55 +125 c ambient operating temperature t a C40 +105 c supply voltages v dd 0 6 volts output voltage v o C0.5 v dd +0.5 volts average forward input current i f - 10 ma average output current i o - 10 ma lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see solder refow temperature profle section recommended operating conditions parameter symbol min. max. units ambient operating temperature t a C40 +105 c supply voltages v dd 4.5 5.5 v 3.0 3.6 v input current (on) i f 4 8 ma supply voltage slew rate [1] sr 0.5 500 v/ms electrical specifcations over recommended temperature (t a = C40c to +105c), 3.0v v dd 3.6v and 4.5 v v dd 5.5 v. all typical specifcations are at t a =+25c , v dd = +3.3v. parameter symbol part number min. typ. max. units test conditions input forward voltage v f 1.2 1.5 1.85 v i f = 6 ma input reverse breakdown voltage bv r 5.0 v i r = 10 a logic high output voltage v oh v dd -1 vdd-0.3 v i f = 6 ma, i o = -4 ma, v dd =3.3 v v dd -1 vdd-0.2 v i f = 6 ma, i o = -4 ma, v dd =5 v logic low output voltage v ol 0.2 0.8 v i f = 0 ma, i o = 4 ma, v dd =3.3 v 0.2 0.8 v i f = 0 ma, i o = 4 ma, v dd =5 v input threshold current i th 1 3 ma i ol = 20 a logic low output supply current i ddl acpl-w70l 4.1 6.5 ma i f = 0 ma acpl-k73l 8.2 13 ma i f = 0 ma logic low output supply current i ddh acpl-w70l 3.8 6 ma i f = 6 ma acpl-k73l 7.6 12 ma i f = 6 ma
7 switching specifcations over recommended temperature (t a = C40c to +105c), 3.0vv dd 3.6v and 4.5 v v dd 5.5 v. all typical specifcations are at t a =+25c, v dd = +3.3v. parameter symbol min. typ. max. units test conditions propagation delay time to logic low output [2] t phl 23 55 ns i f = 6 ma, c l = 15pf cmos signal levels propagation delay time to logic high output [2] t plh 27 55 ns i f = 6 ma, c l = 15pf cmos signal levels pulse width t pw 66.7 ns pulse width distortion [3] |pwd| 0 4 25 ns i f = 6 ma, c l = 15pf cmos signal levels propagation delay skew [4] t psk 40 ns i f = 6 ma, c l = 15pf cmos signal levels output rise time (10% C 90%) t r 3.5 ns i f = 6 ma, c l = 15pf cmos signal levels output fall time (90% - 10%) t f 3.5 ns i f = 0 ma, c l = 15pf cmos signal levels common mode transient immunity at logic high output [5] | cm h | 10 15 kv/s v cm = 1000 v, t a = 25c, i f = 6 ma common mode transient immunity at logic low output [6] | cm l | 10 15 kv/s v cm = 1000 v, t a = 25c, i f = 0 ma package characteristics all typical at t a = 25c. parameter symbol min. typ. max. units test conditions input-output insulation i i-o 1.0 a 45% rh, t = 5 s v i-o = 3 kv dc, t a = 25c input-output momentary withstand voltage v iso (020 option) 5000 v rms rh 50%, t = 1 min., t a = 25c input-output resistance r i-o 10 12 w v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25c notes: 1. slew rate of supply voltage ramping is recommended to ensure no glitch more than 1v to appear at the output pin. 2. t phl propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level on the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level on the rising edge of the v o signal. 3. pwd is defned as |t phl - t plh |. 4. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 5. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 6. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
8 0 2 4 6 8 10 12 -40 t a -temperature- o c i ddh -logic high output supply current-ma 0 5 10 15 20 25 30 35 4 i f ? pulse input current ? ma t p ? propagation delay; pwd-pulse width h distortion ? ns t phl ch1 t phl ch2 t plh ch1 t plh ch2 |pwd| ch1 |pwd| ch2 v dd =5v t a =25 c v dd =5v t a =25 c v dd =5v v dd =3.3v v dd =5v v dd =3.3v 0 2 4 6 8 10 12 -40 t a -temperature- o c t a -temperature- o c i ddl -logic low output supply current- ma 0 5 10 15 20 25 30 35 4 i f ? pulse input current ? ma t p ? propagation delay; pwd-pulse width distortion ? ns t phl ch1 t phl ch2 t plh ch1 t plh ch2 |pwd| ch1 |pwd| ch2 5 6 7 8 9 10 5 6 7 8 9 10 -20 0 20 40 60 80 100 -20 0 20 40 60 80 100 v f - forward voltage-v i f - forward current-ma 0.01 0.1 1 10 1.2 1.3 1.4 1.5 1.6 t a =25c i f v f i th - input threshold current-ma 0.000 0.200 0.400 0.600 0.800 1.000 1.200 1.400 1.600 -40 -20 0 20 40 60 80 100 120 5v 3.3v i ol =20ua figure 1. typical input diode forward characteristic figure 2. typical input threshold current vs. temperature figure 3. typical logic high output supply current vs. temperature for dual channel (acpl-k73l) figure 4. typical logic low output supply current vs. temperature for dual channel (acpl-k73l) figure 5. typical switching speed vs. pulse input current at 5v supply voltage figure 6. typical switching speed vs. pulse input current at 3.3v supply voltage
9 figure 7. typical v f vs. temperature. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -40 t a -temperature- o c v f forward voltage-v -20 0 20 40 60 80 100 application information bypassing and pc board layout the acpl-w70l and acpl-k73l optocouplers are ex - tremely easy to use. acpl-w70l and acpl-k73l provide cmos logic output due to the high-speed cmos ic tech - nology used. the external components required for proper operation are the input limiting resistor and the output bypass ca - pacitor. capacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. propagation delay, pulse-width distortion and propagation delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propa - gate to the output, causing the output to change from high to low (see figure 9). pulse-width distortion (pwd) results when t plh and t phl difer in value. pwd is defned as the diference between t plh and t phl and often pwd is defned as the diference between t plh and t phl and often determines the maxi - mum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact fgure depends on the particular application (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to consider in parallel data applications where synchroni - zation of signals on parallel data lines is a concern. if the parallel data is being sent through a group of opto - couplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at difer - ent times. if this diference in propagation delays is large enough, it will determine the maximum rate at which par - allel data can be sent through the optocouplers. propagation delay skew is defned as the diference be - tween the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temper - ature). as illustrated in figure 10, if the inputs of a group of optocouplers are switched either on or off at the same
10 time, t psk is the diference between the shortest propaga - tion delay, either t phl or t phl , and the longest propagation delay, either t phl or t phl . as mentioned earlier, t psk can de - termine the maximum parallel data transmission rate. figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. the fgure shows data and clock signals at the inputs and outputs of the optocou - plers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew represents the uncertainty of where an edge might be after being sent through an op - tocoupler. data inputs clock data outputs clock t psk t psk 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos figure 9. propagation delay skew waveform figure 10. parallel data transmission example. figure 8. recommended printed circuit board layout 2 3 1 5 4 6 xxx yww i f gnd1 vo v dd c gnd2 acpl-w70l acpl-k73l 7 5 6 8 2 3 4 1 gnd 2 c v dd gnd 1 xxx yww v o2 v o1 i f1 gnd 1 i f2 c = 0 . 0 1 f t o 0 . 1f figure 10 shows that there will be uncertainty in both the data and the clock lines. it is important that these two ar - eas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the t psk specifed optocouplers ofer the advantages of guaranteed specifcations for propagation delays, pulse- width distortion and propagation delay skew over the rec - ommended temperature, and power supply ranges.
11 powering sequence v dd needs to achieve a minimum level of 4.5v before powering up the output connecting component. input limiting resistor acpl-w70l and acpl-k73l are direct current driven (fig - ure 8), and thus eliminate the need for input power supply. to limit the amount of current fowing through the led, it is recommended that a 530ohm resistor is connected in series with anode of led (i.e. pin 1 for acpl-w70l, pin 1 and p4 for acpl-k73l) at 5v input signal. at 3.3v input signal, it is recommended to connect 250ohm resistor in series with anode of led. the recommended limiting re - sistors is based on the assumption that the driver output impedence is 50? (as shown in figure 11). figure 11. connection of peaking capacitor (c peak ) in parallel of the input limiting resistor (r llimit ) to improve speed performance gnd 2 v dd2 0.1f gnd 1 r limit shield v i + - c peak v o r drv = 50 ? figure 12. improvement of t p and pwd with added 100pf peaking capacitor in parallel of input limiting resistor. (i) v dd2 =5v, c peak =100pf, r limit =530? (ii) v dd2 =3.3v, c peak =100pf, r limit =250? 0 5 10 15 20 25 30 35 -40 t plh t |pwd| 0 5 10 15 20 25 30 35 40 t phl -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 with peaking cap without peaking cap t phl t plh t plh t phl t plh with peaking cap without peaking cap |pwd | phl 0 5 10 15 20 25 30 35 -40 t plh t |pwd| 0 5 10 15 20 25 30 35 40 t phl -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 with peaking cap without peaking cap t phl t plh t plh t phl t plh with peaking cap without peaking cap |pwd | phl speed improvement a peaking capacitor can be placed across the input cur - rent limit resistor (figure 11) to achieve enhanced speed performance. the value of the peaking cap is dependent to the rise and fall time of the input signal and supply volt - ages and led input driving current (i f ). figure 12 shows signifcant improvement of propagation delay and pulse with distortion with added 100pf peak capacitor at driv - ing current of 6ma and 5v power supply.
12 common mode rejection for acpl-w70l and acpl-k73l figure 13 shows the recommended driving circuit for the acpl-w70l and acpl-k73l for optimal common-mode re - jection performance. two led-current setting resistors are used instead of one. this is to balance the common mode impedance at led anode and cathode. common-mode transients can capacitively couple from the led anode (or cathode) to the output-side ground causing current to be shunted away from the led (which can be bad if the led is on) or conversely cause current to be injected into the led (bad if the led is meant to be of ). figure14 shows the parasitic capacitances which exists between led anode/ cathode and output ground (c la and c lc ). also shown in figure 14 on the input side is an ac-equivalent circuit. table 1 indicates the directions of i lp and i ln fow depend - ing on the direction of the common-mode transient. for transients occurring when the led is on, common-mode rejection (cm l , since the output is in the low state) de - pends upon the amount of led current drive (i f ). for con - ditions where i f is close to the switching threshold (i th ), cm l also depends on the extent which i lp and i ln balance each other. in other words, any condition where common- mode transients cause a momentary decrease in i f (i.e. when dv cm /dt>0 and |i fp | > |i fn |, referring to table 1) will cause common-mode failure for transients which are fast enough. likewise for common-mode transients which occur when the led is of (i.e. cm h , since the output is high), if an im - balance between i lp and i ln results in a transient i f equal to or greater than the switching threshold of the optocou - pler, the transient signal may cause the output to spike below 2v (which constitutes a cm h failure). by using the recommended circuit in figure 13, good cm r can be achieved. the resistors recommended in figure 13 include both the output impedence of the logic driver cir - cuit and the external limiting resistor. the balanced i led - setting resistors help equalize the common mode voltage change at anode and cathode to reduce the amount by which i led is modulated from transient coupling through c la and c lc . figure 13. recommended drive circuit for acpl-w70l and acpl-k73l for high-cmr g n d 2 v dd2 0 . 1 f g n d 1 r total =300 for v dd =3.3v = 580 for v dd =5v 1/2r t o t a l 1/2r t o t a l v dd1 shield v o 74ls04 or any totem- pole output logic gate figure 14. ac equivalent of acpl-w70l and acpl-k73l gnd 2 v o v dd2 0.1f ? r total shield ? r total i ln i lp c lc c la 15pf 530 ? 3 1 2n3906 (any pnp) v dd 74l504 (any ttl/cmos gate) acpl-w70l led 530 ? 3 1 v dd 74hc00 (or any open-collector /open-drain logic gate) acpl-w70l led 530 ? 3 1 v dd 74hc04 (or any totem-pole output logic gate) acpl-w70l led
13 cmr with other drive circuits cmr performance with drive circuits other than that shown in figure 13 may be enhanced by following these guidelines: 1. use of drive circuits where current is shunted from the led in the led of state (as shown in figures 15 and 16). this is benefcial for good cm h . 2. use of typical i fh = 6ma per datasheet recommendation. using any one of the drive circuits in figures 15-17 with i f = 6 ma will result in a typical cmr of 10 kv/s for acpl- w70l and acpl-k73l, as long as the pc board layout practices are followed. figure 15 shows a circuit which can be used with any totem-pole-output ttl/lsttl/hcmos logic gate. the bufer pnp transistor allows the circuit to be used with logic devices which have low current-sinking capability. it also helps maintain the driving-gate power- supply current at a constant level to minimize ground shifting for other devices connected to the input-supply ground. when using an open-collector ttl or open-drain cmos logic gate, the circuit in figure 16 may be used. when using a cmos gate to drive the optocoupler, the circuit shown in figure 17, where the resistor is recommended to connect to the anode of the led, may be used. figure 15. ttl interface circuit for the acpl-w70l families. gnd 2 v o v dd2 0.1f ? r total shield ? r total i ln i lp c lc c la 15pf 530 ? 3 1 2n3906 (any pnp) v dd 74l504 (any ttl/cmos gate) acpl-w70l led 530 ? 3 1 v dd 74hc00 (or any open-collector /open-drain logic gate) acpl-w70l led 530 ? 3 1 v dd 74hc04 (or any totem-pole output logic gate) acpl-w70l led table 1. efects of common mode pulse direction on transient i led if dv cm /dt is: then i lp flows: and i ln flows: if |i lp | < |i ln |, led i f current is momentarily: if |i lp | < |i ln |, led i f current is momentarily: positive (>0) away from led anode through c la away from led cathode through c lc increased decreased negative (<0) toward led anode through c la toward led cathode through c lc decreased increased figure 16. ttl open-collector/open drain gate drive circuit for acpl-w70l families. gnd 2 v o v dd2 0.1f ? r total shield ? r total i ln i lp c lc c la 15pf 530 ? 3 1 2n3906 (any pnp) v dd 74l504 (any ttl/cmos gate) acpl-w70l led 530 ? 3 1 v dd 74hc00 (or any open-collector /open-drain logic gate) acpl-w70l led 530 ? 3 1 v dd 74hc04 (or any totem-pole output logic gate) acpl-w70l led figure 17. cmos gate drive circuit for acpl-w70l families. gnd 2 v o v dd2 0.1f ? r total shield ? r total i ln i lp c lc c la 15pf 530 ? 3 1 2n3906 (any pnp) v dd 74l504 (any ttl/cmos gate) acpl-w70l led 530 ? 3 1 v dd 74hc00 (or any open-collector /open-drain logic gate) acpl-w70l led 530 ? 3 1 v dd 74hc04 (or any totem-pole output logic gate) acpl-w70l led
v cm 0.1f r limit shield i f a b + - pulse gen. v o gnd2 o v (min.) v dd 0 v switch at a: i = 0 ma f switch at b: i = 6 ma f cm v h cm cm l o v (max.) cm v (peak) v o figure 18. test circuit for common mode transient immunity and typical waveforms. v cm 0.1f r limit shield i f a b + - pulse gen. v o gnd2 o v (min.) v dd 0 v switch at a: i = 0 ma f switch at b: i = 6 ma f cm v h cm cm l o v (max.) cm v (peak) v o for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. av02-1267en - february 2, 2009

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